The present invention relates to a configuration of an ATM switch (ATM being abbreviation of xe2x80x9casynchronous transfer modelxe2x80x9d) for switching ATM signals which are suitable for broadband communication.
Various types of ATM switches have been developed for ATM communication networks. An ATM switch performs cell switching by storing ATM signals (cells) temporarily in a buffer memory (cell buffer memory). As described in xe2x80x9cB-ISDN pictorial readerxe2x80x9d (published by Ohm Sha on January, 1993) pp.74-75, different types of ATM switches have been proposed in accordance with the usage of the cell buffer memory. Among those ATM switches, a shared buffer type ATM switch which shares the cell buffer for all output parts as described in JP-A-2-1669 (corresponding to U.S. Pat. No. RE 34,305 issued on Jul. 6, 1993) is used widely.
Generally, an ATM switch comprises a cell buffer memory for storing cells, and a controller for storing cells in the cell buffer memory with timing control to avoid collision of cells for the same destination. As a cell buffer memory, generally, a static random access memory (SRAM) is used. The SRAM cell buffer requires a simple controller because it is easy in handling. To construct an ATM switch, commonly available SRAMs are externally connected to an LSI having the controller, or an ATM switch LSI having an embedded SRAM for the cell buffer in it is possible with the current device technology.
Recently, data traffic having burst characteristic has increased in ATM networks. A large capacity ATM switch having large cell buffer memories is desired so as to be tolerable against cell loss caused by burst inputs. If the cell buffer of the ATM switch is constructed by external RAMS, the switch throughput is restricted by the access speed of the external RAMs and the number of input/output pins between the LSI and the RAM. In the case of an ATM switch LSI with built-in SRAMS, it is difficult to achieve large cell buffers, because of the limited RAM area of the LSI. In order to solve this problem, it has been proposed to us e a dynamic random access memory (DRAM) as a cell buffer. A DRAM is simple in memory structure and small in mount area, therefore a large-capacity ATM switch with a large cell buffer can be possible using embedded DRAMs in LSI.
As described in xe2x80x9cVLSI Memoryxe2x80x9d published by Baihukan (November, 1994) pp.101-110, a DRAM is constituted by a plurality of banks, each of which has a plurality of memory elements arranged in a matrix form, that is in the column direction and in the row direction. For data writing/reading execution an address of the DRAM is selected on the basis of the three parameters of column, row and bank. The access form in which both the bank and row are not changed but the column is changed is called column access. The access form in which the bank is changed regardless of the column and row is called bank access. The access form in which the bank is not changed but the row is changed regardless of the column is called row access. The difference of these access forms affects the access time and data output time (referred to as irregularity).
Specifically, with respect to the access time, high-speed access is possible in each of the column access and bank access. on the other hand, the row access requires an access time several times as long as that required in the column access or bank access. Further, high-speed data output of an accessed address can be performed in the column access but each of the bank access and row access requires data output time several times as long as that required in the column access. Furthermore, in all the access forms, the data read time in read access is longer than the data write time in write access.
That is, a DRAM can operates at a high speed with the highest-speed continuous access if data writing/reading is performed by continuous column access, that is, continuous read/write address is accessed. A DRAM is a suitable memory for storing burst data such as image data, computer system file data. In these cases, data is burst-written in the memory (continuous address write) and stored until the occasion demands and the data are burst-read from the memory if the occasion demands (continuous address read). On the other hand, applications which requires the three access forms in a random manner, that is, address selection for data reading/writing occurs at random, high-throughput cannot be expected because of the above-mentioned irregularity. Further, after predetermined time, stored data disappears because of electrical characteristic which is peculiar to the DRAM. Accordingly, in order to prevent this data disappearance, execution of data refreshing is required.
In case of a cell buffer memory used in the ATM switch, input cells asynchronously transferred from several input parts are switched to desired output parts which are the destination of the cells. More precisely, the cell buffer memory works as described below. Input cells successively transferred from several input ports are written into cell buffer memory addresses corresponding to the destination output ports and temporarily stored in the cell buffer. Then they are successively read out to the designated output ports, at intervals of a time matched with the throughput of the output lines. The destinations (switching destinations) of the input cells successively transferred to the switch are not determined by the switch, but determined by communication partners designated by the transmission side. Further, the interval and time of the arrival of cells are determined at random because the interval and time of the arrival of cells are asynchronous and depend on the traffic characteristic of the lines.
That is, in the cell buffer memory, inputting/outputting of cells having random destinations is executed substantially continuously based on random addresses. Furthermore, the random state of the cell input/output timing and address in the cell buffer memory varies randomly in accordance with the traffic characteristic in the network. Even if a predetermined rule is decided in advance to control the input/output of the cell buffer memory, the random state of the cell input/output timing and address varies in accordance with the state of the communication network.
If a DRAM is used as a cell buffer memory which has the aforementioned characteristic, the aforementioned three access forms occur at random. Accordingly, the irregularity of access causes a cell loss because of a possibility that the shortage of cell switching time. To avoid this, cells should be switched in the timing based on the consideration of the longest access time and longest data input/output delay of the DRAM. However, if the switching speed is reduced to avoid such a cell loss, switching throughput is lowered. Further, if the data refreshing operation is performed at suitable time intervals with cell inputting/outputting is executed substantially continuously, throughput is limited more.
Specifically, the switching speed considering the longest access time and longest data input/output delay of the DRAM is about ten-times longer than that of the SRAM. Accordingly, it is difficult to use a DRAM simply as an ATM switch cell buffer memory which requires high-throughput.
In order to solve the aforementioned problem, an object of the present invention is to provide an ATM switch which is large in capacity and high in throughput and which reduces cell loss by having a large cell buffer. Specifically, the object is to provide an ATM switch which uses a DRAM as a cell buffer memory, which is large in capacity and high in throughput with low cell loss possibility.
Another object of the present invention is to provide means and method for absorbing variation in access time and delay time caused by the different access forms of a DRAM, and to provide a switch which uses a DRAM having the above means and method, which is large in capacity and high in throughput with low cell loss possibility. That is, this object is to provide means and method for using a DRAM as a cell buffer memory of an ATM switch which is large in capacity and 25 high throughput with low cell loss probability.
More specifically, a further object of the present invention is to provide means and method for absorbing variation in access time and data write time caused by random write access of a DRAM memory and to provide an ATM switch with large capacity, high throughput, and low cell loss probability by using the means and method.
Further, still another object of the present invention is to provide means and method for absorbing variation in access time and data read delay caused by random read access of a DRAM memory and to provide an ATM switch with large capacity, high throughput, and low cell loss probability by using the means and method.
A still further object of the present invention is to provide means for giving refreshing timing which is necessary in a case of using a DRAM as a cell buffer memory to provide a high-throughput large-capacity ATM switch with the secure refreshing operation to prevent a cell loss in the switch.
In order to solve the aforementioned problem, the present invention provides an ATM switch to receive ATM cells from several input ports, then switch and output the cells to one of output ports comprising: a first memory using a DRAM for storing the cells; a second memory using an SRAM for switching (temporarily storing) the input cells before the input cells are transferred to the first memory; and a controller for generating write/read address and timing signals for the first and second memories. Further, the controller is configured to generate read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on the access address of the first memory into account. In such a configuration, the cells switched by the second memory are further stored in the first memory. Consequently, a high-throughput large-capacity ATM switch is achieved by absorbing the variation in access time or delay time based on the access address of the first memory.
More specifically, the controller is constituted by a first address generating circuit for generating access addresses of the first memory, a second address generating circuit for generating access addresses of the second memory, a judgment circuit for judging the idle state of the second memory, and a timing circuit for generating, based on the output of the first address generating circuit, output timing signals for the first and second address generating circuits in accordance with variation in access time or delay time based on the access address of the first memory. In such a manner, the cells switched (temporarily stored) by the second memory are stored in the first memory again. Consequently, a high-throughput large-capacity ATM switch is achieved by absorbing variation in access time or delay time based on the access address of the first memory. Further, the controller performs controlling so that cell writing in the first memory and cell reading from the second memory are performed at a higher speed than the speed of cell writing in the second memory. Consequently, the ATM switch is be transferred to the first memory and variation in access time or delay time based on the access address of the first memory is absorbed.
A third memory using an SRAM with high-speed random read/write access may be further provided in the rear of the first memory using a DRAM. In such a manner, the ATM switch is configured so that variations in cell output timing to output ports are absorbed.
Furthermore, a refreshing circuit is provided in the controller so that a refreshing operation can be performed to prevent the stored cell data from disappearing. The ATM switch is configured so as to heighten the access speed of the first memory. As a result, the refreshing operation is executed in a vacant timing during cell transfer from the second memory to the first memory. Incidentally, because idle cells supplied to the ATM switch periodically are never switched, the ATM switch is also configured so that the refreshing operation can be performed in the first memory in the timing of the idle cells.